UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 358
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UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 358 of 1171
- Download datasheet (8Mb)
78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Figure 7-11. Format of Peripheral Enable Registers 0 and 1 (PER0, PER1) (78K0R/KF3-L, 78K0R/KG3-L) (2/2)
Address: F00F0H
Address: F00F1H
PER1
Symbol
Symbol
PER0
Note
Caution Be sure to clear bit 6 of the PER0 register and bits 0, and 2 to 7 of the PER1 register to 0.
Note
SAU2EN
SAU0EN
TAU1EN
TAU0EN
RTCEN
<7>
7
0
0
1
0
1
0
1
0
1
PER1 register is only mounted in the
After reset: 00H
After reset: 00H
Note
Stops input clock supply.
• SFR used by the serial array unit 0 cannot be written.
• The serial array unit 0 is in the reset status.
Supplies input clock.
• SFR used by the serial array unit 0 can be read and written.
Stops input clock supply.
• SFR used by timer array unit 1 cannot be written.
• Timer array unit 1 is in the reset status.
Supplies input clock.
• SFR used by timer array unit 1 can be read and written.
Stops input clock supply.
• SFR used by timer array unit 0 cannot be written.
• Timer array unit 0 is in the reset status.
Supplies input clock.
• SFR used by timer array unit 0 can be read and written.
Stops input clock supply.
• SFR used by the serial array unit 2 cannot be written.
• The serial array unit 2 is in the reset status.
Supplies input clock.
• SFR used by the serial array unit 2 can be read and written.
6
0
6
0
R/W
R/W
ADCEN
<5>
5
0
Control of serial array unit 0 input clock supply
Control of serial array unit 2 input clock supply
Control of timer array unit 1 input clock supply
Control of timer array unit 0 input clock supply
IICAEN
<4>
4
0
μ
PD78F1027, 78F1028, 78F1029, and 78F1030.
SAU1EN
<3>
3
0
CHAPTER 7 CLOCK GENERATOR
SAU0EN
<2>
2
0
SAU2EN
TAU1EN
<1>
<1>
Note
TAU0EN
<0>
0
0
358
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