UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 1104
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UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
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Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp
Remarks 1.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
SCKp cycle time
SCKp high-/low-level width
SIp setup time
(to SCKp↑)
SIp hold time
(from SCKp↑)
Delay time from SCKp↓ to
SOp output
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
(T
A
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
4. C is the load capacitance of the SOp output lines.
= −40 to +85°C, 1.8 V ≤ V
Parameter
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
pin by using port input mode register g (PIMg) and port output mode register g (POMg).
2.
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 1
Note 3
Note 2
(Operation clock to be set by the CKSmn bit of the SMRmn register. m: Unit number (m = 0 to 2),
n: Channel number (n = 0 to 2))
p: CSI number (p = 00, 01, 10, 20, 40, 41), g: PIM and POM number (g = 0, 1, 14)
f
MCK
: Serial array unit operation clock frequency
t
t
t
t
t
t
KCY2
KH2
KL2
SIK2
KSI2
KSO2
Symbol
CHAPTER 31 ELECTRICAL SPECIFICATIONS (78K0R/KF3-L, 78K0R/KG3-L)
,
DD
= EV
4.0 V ≤ V
1.8 V ≤ V
V
C = 30 pF
DD0
= EV
DD
DD
Note 4
DD1
≤ 5.5 V
< 4.0
Conditions
≤ 5.5 V, V
4.0 V ≤ V
2.7 V ≤ V
1.8 V ≤ V
16 MHz < f
f
MCK
≤ 16 MHz
DD
DD
DD
SS
≤ 5.5 V
< 4.0 V
< 2.7 V
= EV
MCK
SS0
1/f
= EV
t
6/f
8/f
6/f
KCY2
MIN.
MCK
80
MCK
MCK
MCK
+50
SS1
/2
= AV
TYP.
SS
= 0 V)
2/f
2/f
2/f
MAX.
MCK
MCK
MCK
+125
+45
+57
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
1104
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