UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 831
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UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
The meanings of <7> to <15> in (3) Data ~ data ~ stop condition in Figure 15-32 are explained below.
Remark <1> to <15> in Figure 15-32 represent the entire procedure for communicating data using the I
<7> When data transfer is complete, the slave device sends an ACK by hardware to the master device. The
<8> The master device and slave device set a wait status (SCL0 = 0) at the falling edge of the 9th clock, and
<9> The master device writes the data to transmit to the IICA shift register (IICA) and releases the wait status
<10> The slave device reads the received data and releases the wait status (WREL = 1). The master device then
<11> When data transfer is complete, the slave device sends an ACK by hardware to the master device. The
<12> The master device and slave device set a wait status (SCL0 = 0) at the falling edge of the 9th clock, and
<13> The slave device reads the received data and releases the wait status (WREL = 1).
<14> After a stop condition trigger is set, the bus data line is cleared (SDA0 = 0) and the bus clock line is set
<15> When a stop condition is generated, the slave device detects the stop condition and issues an interrupt
ACK is detected by the master device (ACKD = 1) at the rising edge of the 9th clock.
both the master device and slave device issue an interrupt (INTIICA: end of transfer).
that it set by the master device.
starts transferring data to the slave device.
ACK is detected by the master device (ACKD = 1) at the rising edge of the 9th clock.
both the master device and slave device issue an interrupt (INTIICA: end of transfer).
(SCL0 = 1). The stop condition is then generated by setting the bus data line (SDA0 = 1) after the stop
condition setup time has elapsed.
(INTIICA: stop condition).
Figure 15-32 (1) Start condition ~ address ~ data shows the processing from <1> to <6>, Figure 15-32
(2) Address ~ data ~ data shows the processing from <3> to <10>, and Figure 15-32 (3) Data ~ data ~
stop condition shows the processing from <7> to <15>.
CHAPTER 15 SERIAL INTERFACE IICA
2
C bus.
831
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