UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 322
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 322 of 1171
- Download datasheet (8Mb)
78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Symbol
PM11
PM12
PM13
PM14
PM15
PM0
PM1
PM2
PM3
PM4
PM5
PM6
PM7
PM8
PM9
Caution
PM157
PMmn
PM17
PM27
PM47
PM57
PM67
PM77
PM87
register, bits 2 to 7 of the PM11 register, bits 1 to 7 of the PM12 register, bits 2 to 7 of the PM13
register, and bits 6 and 7 of the PM14 register to “1”. And be sure to set bit 0 of the PM13 register to
“0”.
Be sure to set bit 7 of the PM0 register, bits 2 to 7 of the PM3 register, bits 0 and 2 to 7 of the PM9
0
1
7
1
1
1
1
1
1
1
Output mode (output buffer on)
Input mode (output buffer off)
PM156
PM06
PM16
PM26
PM46
PM56
PM66
PM76
PM86
6
1
1
1
1
1
1
PM145
PM155
Figure 6-53. Format of Port Mode Register (78K0R/KG3-L)
PM05
PM15
PM25
PM45
PM55
PM65
PM75
PM85
5
1
1
1
1
1
PM144
PM154
PM04
PM14
PM24
PM44
PM54
PM64
PM74
PM84
4
1
1
1
1
1
CHAPTER 6 PORT FUNCTIONS (78K0R/KF3-L, 78K0R/KG3-L)
PM143
PM153
PM03
PM13
PM23
PM43
PM53
PM63
PM73
PM83
3
1
1
1
1
1
(m = 0 to 9, 11 to 15; n = 0 to 7)
Pmn pin I/O mode selection
PM142
PM152
PM02
PM12
PM22
PM42
PM52
PM62
PM72
PM82
2
1
1
1
1
1
PM111
PM131
PM141
PM151
PM01
PM11
PM21
PM31
PM41
PM51
PM61
PM71
PM81
PM91
1
1
PM110
PM120
PM140
PM150
PM00
PM10
PM20
PM30
PM40
PM50
PM60
PM70
PM80
0
1
0
FFF2BH
FFF2CH
FFF2DH
FFF2EH
Address
FFF20H
FFF21H
FFF22H
FFF23H
FFF24H
FFF25H
FFF26H
FFF27H
FFF28H
FFF29H
FFF2FH
After reset
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FEH
FFH
FFH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
322
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