UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 256
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UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
6.2.1 Port 0
Notes 1. TI00 and TO00 are shared with P53 and P52, respectively, in the 78K0R/KF3-L.
mode register 0 (PM0). When the P00 to P06 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 0 (PU0).
port input mode register 0 (PIM0).
output mode register 0 (POM0).
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
P00/TI00
P01/TO00
P02/SO10/TxD1
P03/SI10/RxD1/SDA10
P04/SCK10/SCL10
P05/TI05/TO05
P06/TI06/TO06
Port 0 is an I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port
Input to the P03 and P04 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units using
Output from the P02 to P04 pins can be specified as N-ch open-drain output (V
This port can also be used for timer I/O, serial interface data I/O, and clock I/O.
Reset signal generation sets port 0 to input mode.
Figures 6-1 to 6-5 show block diagrams of port 0.
Cautions 1. To use P01/TO00 as a general-purpose port, set bit 0 (TO00) of timer output register 0 (TO0) and
2. TI05/TO05 and TI06/TO06 are shared with P46 and P131, respectively, in the 78K0R/KG3-L.
2. To use P02/SO10/TxD1, P03/SI10/RxD1/SDA10, or P04/SCK10/SCL10 as a general-purpose port,
3. To use P05/TI05/TO05 or P06/TI06/TO06 as a general-purpose port, set bits 5 and 6 (TO05, TO06)
bit 0 (TOE00) of timer output enable register 0 (TOE0) to “0”, which is the same as their default
status setting.
note the serial array unit 0 setting. For details, refer to the following tables.
• Table 14-11 Relationship Between Register Settings and Pins (Channel 2 of Unit 0: CSI10,
• Table 14-12 Relationship Between Register Settings and Pins (Channel 3 of Unit 0: UART1
of timer output register 0 (TO0) and bits 5 and 6 (TOE05, TOE06) of timer output enable register 0
(TOE0) to “0”, which is the same as their default status setting.
UART1 Transmission, IIC10)
Reception)
(
μ
PD78F10xx: xx = 10, 11, 12,
78K0R/KF3-L
27, 28)
−
−
Note 1
Note 1
√
√
√
√
√
CHAPTER 6 PORT FUNCTIONS (78K0R/KF3-L, 78K0R/KG3-L)
(
μ
PD78F10xx: xx = 13, 14,
78K0R/KG3-L
P05
P06
29, 30)
√
√
√
√
√
Note 2
Note 2
DD
tolerance) in 1-bit units using port
256
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