UPD78F1001GB-GAF-AX Renesas Electronics America, UPD78F1001GB-GAF-AX Datasheet - Page 851
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UPD78F1001GB-GAF-AX
Manufacturer Part Number
UPD78F1001GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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- Download datasheet (8Mb)
78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(2) DMA RAM address register n (DRAn)
Address: FFFB2H, FFFB3H (DRA0), FFFB4H, FFFB5H (DRA1)
(n = 0, 1)
This is a 16-bit register that is used to set a RAM address that is the transfer source or destination of DMA
channel n.
Addresses of the internal RAM area other than the general-purpose registers (FF900H to FFEDFH in the case of
the
Set the lower 16 bits of the RAM address.
This register is automatically incremented when DMA transfer has been started. It is incremented by +1 in the 8-
bit transfer mode and by +2 in the 16-bit transfer mode. DMA transfer is started from the address set to this
DRAn register. When the data of the last address has been transferred, the DRAn register stops with the value of
the last address +1 in the 8-bit transfer mode, and the last address +2 in the 16-bit transfer mode.
In the 16-bit transfer mode, the least significant bit is ignored and is treated as an even address.
The DRAn register can be read or written in 8-bit or 16-bit units. However, it cannot be written during DMA
transfer.
Reset signal generation clears this register to 0000H.
Remark
DRAn
μ
PD78F1001, 78F1004, and 78F1007) can be set to this register.
n: DMA channel number (n = 0, 1)
15
14
Figure 17-2. Format of DMA RAM Address Register n (DRAn)
13
DRA0H: FFFB3H
DRA1H: FFFB5H
12
11
10
9
8
After reset: 0000H
7
6
CHAPTER 17 DMA CONTROLLER
5
DRA0L: FFFB2H
DRA1L: FFFB4H
R/W
4
3
2
1
0
851
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