DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 945

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

User operation
User operation
User operation
LSI operation
LSI operation
LSI operation
(MSB first)
(1) When 8-bit data length is selected (SSRDR0 is valid) with CPOS = 0 and CPHS = 0
(2) When 16-bit data length is selected (SSRDR0 and SSRDR1 are valid) with CPOS = 0 and CPHS = 0
(MSB first)
(3) When 32-bit data length is selected (SSRDR0 to SSRDR3 are valid) with CPOS = 0 and CPHS = 0
(LSB first)
(LSB first)
SSCK
RDRF
SSCK
RDRF
SSCK
RDRF
SCS
SCS
SCS
SSI
SSI
SSI
SSI
SSI
Figure 17.7 Example of Reception Operation (SSU Mode)
Dummy-readSSRDR0
Dummy-readSSRDR0
Dummy-read SSRDR0
Bit
Bit
Bit
Bit
Bit
0
7
0
7
0
SSRDR3
SSRDR0
Bit
SSRDR0 (LSB first transmission)
Bit
Bit
to
to
1
1
6
Bit
Bit
Bit
Bit
Bit
2
5
7
0
2
SSRDR1
SSRDR0
1 frame
Bit
Bit
Bit
Bit
Bit
3
3
4
0
7
SSRDR2
SSRDR1
Bit
Bit
Bit
to
to
4
4
3
1 frame
Bit
Bit
Bit
Bit
Bit
5
5
2
7
0
Section 17 Synchronous Serial Communication Unit (SSU)
Bit
Bit
Bit
Bit
Bit
RXI interrupt
6
6
0
1
7
generated
SSRDR1
SSRDR2
1 frame
Bit
Bit
Bit
to
to
7
7
0
Read SSRDR0
Bit
Bit
Bit
Bit
7
7
0
0
Bit
Bit
Bit
Bit
6
0
7
1
SSRDR0
SSRDR3
Bit
Bit
Bit
7
to
to
5
2
RXI interrupt generated
Rev. 3.00 May 17, 2007 Page 887 of 1582
SSRDR0 (MSB first transmission)
SSRDR0
SSRDR1
Bit
Bit
Bit
Bit
Bit
6
4
7
0
3
Bit
Bit
Bit
5
3
4
1 frame
RXI interrupt generated
Bit
Bit
Bit
4
2
5
Bit
Bit
Bit
3
1
6
Bit
Bit
Bit
2
7
0
RXI interrupt
Bit
1
generated
Bit
0
REJ09B0181-0300