DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 256

IC SUPERH MCU FLASH 112LQFP

DF70845AD80FPV

Manufacturer Part Number
DF70845AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet

Specifications of DF70845AD80FPV

Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
32KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF70845AD80FPV
Manufacturer:
TAIYO
Quantity:
40 000
Part Number:
DF70845AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 8 Data Transfer Controller (DTC)
8.5.5
In block transfer mode, data are transferred in block units in response to a single activation
request. Either the transfer source or the transfer destination is designated as a block area by the
DTS bit in MRB.
The block size is 1 to 256 bytes (1 to 256 words, or 1 to 256 longwords). When the block data
transfer of one block ends, the block size counter (CRAL) and address register (SAR when DTS =
1 or DAR when DTS = 0) specified as the block area is restored to the initial state. The other
address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be
specified. When the specified number of transfers ends, an interrupt is requested to the CPU.
Table 8.8 lists the register function in block transfer mode. Figure 8.8 shows the memory map in
block transfer mode.
Table 8.8
Note:
Rev. 3.00 May 17, 2007 Page 198 of 1582
REJ09B0181-0300
Register Function
SAR
DAR
CRAH
CRAL
CRB
*
Block Transfer Mode
Source address
Destination address
Block size storage
Block size counter
Block transfer counter
Transfer information writeback is skipped.
Register Function in Block Transfer Mode
Written Back Value
DTS = 0: Incremented/decremented/fixed*
DTS = 1: SAR initial value
DTS = 0: DAR initial value
DTS = 1: Incremented/decremented/fixed*
CRAH
CRAH
CRB − 1

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