DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 164

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 6 Interrupt Controller (INTC)
Figure 6.1 shows a block diagram of the INTC.
Rev. 3.00 May 17, 2007 Page 106 of 1582
REJ09B0181-0300
[Legend]
UBC:
WDT:
CMT:
SCIF:
SCI:
DMAC:
MTU2:
MTU2S: Multi-function timer pulse unit 2S
A/D:
I
POE:
SSU:
DTC:
2
MTU2S
C2:
DMAC
MTU2
WDT
SCIF
CMT
UBC
POE
SSU
BSC
I
A/D
SCI
2
C2
Direct memory access controller
Synchronous serial communication unit
Data transfer controller
User break controller
Watchdog timer
Compare match timer
Serial communication interface with FIFO
Multi-function timer pulse unit 2
A/D converter
Port output enable
Serial communication interface
I
2
C bus interface 2
CHCR[11:8]
DTC
DTCERA to
IRQOUT
DTCERE
DMAC
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
NMI
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
Figure 6.1 Block Diagram of INTC
IRQCR
IRQSR
ICR0
control
Input
Module bus
INTC
BSC:
ICR0:
IRQCR:
IRQSR:
IPRA to IPRF,
IPRH to IPRM:
SR:
CHCR:
DTCERA to DTCERE: DTC enable registers A to E
IPRA to IPRF,
IPRH to IPRM
IPR
Status register
Interrupt control register 0
Bus state controller
IRQ status register
DMA channel control register
IRQ control register
Interrupt priority registers A to F and H to M
interface
parator
Com-
Bus
I3 I2 I1 I0
Interrupt
request
CPU
SR