DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 858

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 16 Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 May 17, 2007 Page 800 of 1582
REJ09B0181-0300
Bit
4
3
Bit Name
RE
REIE
Initial
value
0
0
R/W
R/W
R/W
Description
Receive Enable
Enables or disables the SCIF serial receiver.
0:Receiver disabled*
1: Receiver enabled*
Note: 1. Clearing RE to 0 does not affect the receive
Receive Error Interrupt Enable
Enables or disables the receive-error (ERIF) interrupts
and break (BRIF) interrupts. The setting of REIE bit is
valid only when RIE bit is set to 0.
0: Receive-error interrupt (ERIF) and break interrupt
1: Receive-error interrupt (ERIF) and break interrupt
Note: * ERIF or BRIF interrupt requests can be cleared
(BRIF) requests are disabled*
(BRIF) requests are enabled
2. Serial reception starts when a start bit is
by reading the ER, BR or ORER flag after it
has been set to 1, then clearing the flag to 0, or
by clearing RIE and REIE to 0. Even if RIE is
set to 0, when REIE is set to 1, ERIF or BRIF
interrupt requests are enabled.
flags (DR, ER, BRK, RDF, FER, PER, and
ORER). These flags retain their previous
values.
detected in asynchronous mode, or
synchronous clock input is detected in clock
synchronous mode. Select the receive format
in SCSMR and SCFCR and reset the receive
FIFO before setting RE to 1.
1
2