DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 190

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 6 Interrupt Controller (INTC)
6.8
The following data transfers can be done using interrupt request signals:
• Activate DMAC only; CPU interrupts do not occur
• Activate DTC only; CPU interrupts depend on DTC settings
Interrupt sources that are assigned for DMAC activation sources are masked without being input
to the INTC. The mask condition is as follows:
Mask condition = Interrupt source select (CH0) + interrupt source select (CH1) + interrupt source
select (CH2) + interrupt source select (CH3)
The INTC masks a CPU interrupt when the corresponding DTCE bit is 1. The conditions for
clearing DTCE and interrupt source flag are shown below.
DTCE clear condition = DTC transfer end • DTCECLR
Interrupt source flag clear condition = DTC transfer end • DTCECLR + DMAC transfer end
where DTCECLR = DISEL + counter 0
Figures 6.5 and 6.6 show control block diagrams.
Rev. 3.00 May 17, 2007 Page 132 of 1582
REJ09B0181-0300
IRQ pin
Data Transfer with Interrupt Request Signals
IRQ edge detector
(in standby mode)
IRQ detection
Figure 6.5 IRQ Interrupt Control Block Diagram
IRQ flag clear by DTC
Standby cancel
DTCER
determination
DTCE clear
Interrupt priority
determination
Interrupt controller
Standby control
Interrupt request to CPU
DTC activation
request
DTCECLR
Transfer end
DTC