DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 1391

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

26.3.4
STBCR4 is an 8-bit readable/writable register that controls the operation of modules in power-
down mode.
Bit
5
4
3
2
1, 0
Standby Control Register 4 (STBCR4)
Bit Name
MSTP13
MSTP12
MSTP11
MSTP10

Initial value:
Initial
Value
1
1
1
1
All 1
R/W:
Bit:
MSTP
R/W
23
7
1
R/W
R/W
R/W
R/W
R/W
R
MSTP
R/W
22
6
1
Description
Module Stop Bit 13
When this bit is set to 1, the supply of the clock to the
SCI_2 is halted.
0: SCI_2 operates
1: Clock supply to SCI_2 halted
Module Stop Bit 12
When this bit is set to 1, the supply of the clock to the
SCI_1 is halted.
0: SCI_1 operates
1: Clock supply to SCI_1 halted
Module Stop Bit 11
When this bit is set to 1, the supply of the clock to the
SCI_0 is halted.
0: SCI_0 operates
1: Clock supply to SCI_0 halted
Module Stop Bit 10
When this bit is set to 1, the supply of the clock to the
SSU is halted.
0: SSU operates
1: Clock supply to SSU halted
Reserved
These bits are always read as 1. The write value should
always be 1.
MSTP
R/W
21
5
1
R
4
1
-
R
3
1
-
Rev. 3.00 May 17, 2007 Page 1333 of 1582
MSTP
R/W
18
2
1
MSTP
R/W
17
1
1
Section 26 Power-Down Modes
MSTP
R/W
16
0
1
REJ09B0181-0300