DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 839

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

15.5
The SCI has four interrupt sources: transmit end (TEI), receive error (ERI), receive-data-full
(RXI), and transmit-data-empty (TXI) interrupt requests.
Table 15.17 shows the interrupt sources. The interrupt sources are enabled or disabled by means of
the TIE, RIE, and TEIE bits in SCSCR and the EIO bit in SCSPTR. A separate interrupt request is
sent to the interrupt controller for each of these interrupt sources.
When the TDRE flag in the serial status register (SCSSR) is set to 1, a TDR empty interrupt
request is generated. This request can be used to activate the direct memory access controller
(DMAC) or data transfer controller (DTC) to transfer data. The TDRE flag is automatically
cleared to 0 when data is written to the transmit data register (SCTDR) through the DMAC or
DTC.
When the RDRF flag in SCSSR is set to 1, an RDR full interrupt request is generated. This request
can be used to activate the DMAC or DTC to transfer data. The RDRF flag is automatically
cleared to 0 when data is read from the receive data register (SCRDR) through the DMAC or
DTC.
When the ORER, FER, or PER flag in SCSSR is set to 1, an ERI interrupt request is generated.
This request cannot be used to activate the DMAC or DTC. When processing the received data
through the DMAC or DTC and handling the receive error by an interrupt requested to the CPU,
set the RIE bit to 1 and set the EIO bit in SCSPTR to 1 to issue an interrupt to the CPU only when
a receive error is detected. If the EIO bit is cleared to 0, an interrupt is issued to the CPU even
when correct data is received.
When the TEND flag in SCSSR is set to 1, a TEI interrupt request is generated. This request
cannot be used to activate the DMAC or DTC.
The TXI interrupt indicates that transmit data can be written, and the TEI interrupt indicates that
transmission has been completed.
Table 15.17 SCI Interrupt Sources
Interrupt Source
ERI
RXI
TXI
TEI
SCI Interrupt Sources and DMAC/DTC
Description
Interrupt caused by receive error (ORER, FER, or
PER)
Interrupt caused by receive data full (RDRF)
Interrupt caused by transmit data empty (TDRE)
Interrupt caused by transmit end (TENT)
Section 15 Serial Communication Interface (SCI)
Rev. 3.00 May 17, 2007 Page 781 of 1582
DMAC/DTC Activation
Not possible
Possible
Possible
Not possible
REJ09B0181-0300