DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 757

IC SUPERH MCU FLASH 112LQFP

DF70845AD80FPV

Manufacturer Part Number
DF70845AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet

Specifications of DF70845AD80FPV

Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
32KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF70845AD80FPV
Manufacturer:
TAIYO
Quantity:
40 000
Part Number:
DF70845AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
13.3.8
POECR2 is a 16-bit readable/writable register that controls high-impedance state of the pins.
Initial value:
Bit
15
14
Note:
R/W:
Bit:
*
Can be modified only once after a power-on reset.
Bit Name
MTU2P1CZE
Port Output Enable Control Register 2 (POECR2)
15
R
0
-
R/W* R/W* R/W*
P1CZE
MTU2
14
1
P2CZE
MTU2
13
1
Initial
value
0
1
P3CZE
MTU2
12
1
11
R
0
-
R
R/W*
R/W
MTU2S
R/W* R/W* R/W*
P1CZE
10
1
MTU2S
P2CZE
9
1
Reserved
This bit is always read as 0. The write value should
always be 0.
MTU2 Port 1 Output Comparison/High-Impedance
Enable
This bit specifies whether to compare output levels for
the MTU2 high-current PE9/TIOC3B and
PE11/TIOC3D pins and to place them in high-
impedance state when the OSF1 bit is set to 1 while
the OCE1 bit is 1 or when any one of the POE0F,
POE1F, POE2F, POE3F, and MTU2CH34HIZ bits is
set to 1.
0: Does not compare output levels or place the pins in
1: Compares output levels and places the pins in
Description
high-impedance state
high-impedance state
MTU2S
P3CZE
8
1
R
7
0
-
R/W* R/W* R/W*
MTU2S
P4CZE
Rev. 3.00 May 17, 2007 Page 699 of 1582
6
0
Section 13 Port Output Enable (POE)
MTU2S
P5CZE
5
0
MTU2S
P6CZE
4
0
R
3
0
-
REJ09B0181-0300
R/W* R/W* R/W*
MTU2S
P7CZE
2
0
MTU2S
P8CZE
1
0
MTU2S
P9CZE
0
0

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