DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 392

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
Relationship between Refresh Requests and Bus Cycles: If a refresh request occurs during bus
cycle execution, the refresh cycle must wait for the bus cycle to be completed. If a refresh request
occurs while the bus is released by the bus arbitration function, the refresh will not be executed
until the bus mastership is acquired. This LSI has the IRQOUT pin to request the bus while
waiting for refresh execution. This LSI continues to assert IRQOUT (low level) until the bus is
acquired.
If a new refresh request occurs while waiting for the previous refresh request, the previous refresh
request is deleted. To refresh correctly, a bus cycle longer than the refresh interval or the bus
mastership occupation must be prevented from occurring.
If a bus mastership is requested during self-refresh, the bus will not be released until the self-
refresh is cleared.
Power-On Sequence: In order to use SDRAM, mode setting must first be made for SDRAM after
powering on. To perform SDRAM initialization correctly, the bus state controller registers must
first be set, followed by a write to the SDRAM mode register. In SDRAM mode register setting,
the address signal value at that time is latched by a combination of the CSn, RASU, RASL,
CASU, CASL, and RDWR signals. If the value to be set is X, the bus state controller provides for
value X to be written to the SDRAM mode register by performing a word-write to address
H'FFF84000 + X for area 2 SDRAM, and to address H'FFF85000 + X for area 3 SDRAM. In this
operation, the write data is ignored. To set burst read/single write (burst length 1), burst read/burst
write (burst length 1), CAS latency 2 and 3, wrap type = sequential, and burst length 1 supported
by the LSI, arbitrary data is written in a word-size access to the addresses shown in table 9.27. In
this time, 0 is output at the external address pins of A12 and later.
Rev. 3.00 May 17, 2007 Page 334 of 1582
REJ09B0181-0300