DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 375

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Burst Read: A burst read occurs in the following cases with this LSI.
• Access size in reading is larger than data bus width
• 16-byte transfer in DMAC
This LSI always accesses SDRAM with burst length 1. For example, read access of burst length 1
is performed consecutively 4 times to read 16-byte continuous data from SDRAM that is
connected to a 32-bit data bus. This access is called number of bursts 4.
Table 9.26 shows the relationship between the access size and the number of bursts.
Table 9.26 Relationship between Access Size and Number of Bursts
Figures 9.17 and 9.18 show a timing chart in burst read. In burst read, an ACTV command is
output in the Tr cycle, the READ command is issued in the Tc1 to Tc3 cycles, the READA
command is issued in the Tc4 cycle, and the read data is received at the rising edge of the external
clock (CK) in the Td1 to Td4 cycles. The Tap cycle is used to wait for the completion of an auto-
precharge induced by the READ command in the SDRAM. In the Tap cycle, a new command will
not be issued to the same bank. However, access to another CS space or another bank in the same
SDRAM space is enabled. The number of Tap cycles is specified by the WTRP1 and WTRP0 bits
in CS3WCR.
In this LSI, wait cycles can be inserted by specifying each bit in CSnWCR to connect the SDRAM
in variable frequencies. Figure 9.18 shows an example in which wait cycles are inserted. The
number of cycles from the Tr cycle where the ACTV command is output to the Tc1 cycle where
the READA command is output can be specified using the WTRCD1 and WTRCD0 bits in
CS3WCR. If the WTRCD1 and WTRCD0 bits specify one cycle or more, a Trw cycle where the
NOP command is issued is inserted between the Tr cycle and Tc1 cycle. The number of cycles
from the Tc1 cycle where the READA command is output to the Td1 cycle where the read data is
Bus Width
16 bits
32 bits
Access Size
8 bits
16 bits
32 bits
16 bytes
8 bits
16 bits
32 bits
16 bytes
Rev. 3.00 May 17, 2007 Page 317 of 1582
Section 9 Bus State Controller (BSC)
1
1
2
8
1
1
1
4
Number of Bursts
REJ09B0181-0300