DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 20

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

16.5 SCIF Interrupt Sources and DTC....................................................................................... 850
16.6 Serial Port Register (SCSPTR) and SCIF Pins .................................................................. 851
16.7 Usage Notes ....................................................................................................................... 854
Section 17 Synchronous Serial Communication Unit (SSU) ............................ 859
17.1 Features.............................................................................................................................. 859
17.2 Input/Output Pins............................................................................................................... 861
17.3 Register Descriptions......................................................................................................... 862
17.4 Operation ........................................................................................................................... 876
17.5 SSU Interrupt Sources and DTC........................................................................................ 898
17.6 Usage Notes ....................................................................................................................... 899
Rev. 3.00 May 17, 2007 Page xx of lviii
16.4.3 Clock Synchronous Mode..................................................................................... 842
16.7.1 SCFTDR Writing and TDFE Flag ........................................................................ 854
16.7.2 SCFRDR Reading and RDF Flag ......................................................................... 854
16.7.3 Break Detection and Processing ........................................................................... 855
16.7.4 Sending a Break Signal......................................................................................... 855
16.7.5 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) ...... 855
16.7.6 Module Standby Mode Setting ............................................................................. 857
16.7.7 Note on Using DTC .............................................................................................. 857
16.7.8 FER Flag and PER Flag of Serial Status Register (SCFSR)................................. 857
17.3.1 SS Control Register H (SSCRH) .......................................................................... 863
17.3.2 SS Control Register L (SSCRL) ........................................................................... 865
17.3.3 SS Mode Register (SSMR) ................................................................................... 866
17.3.4 SS Enable Register (SSER) .................................................................................. 867
17.3.5 SS Status Register (SSSR).................................................................................... 869
17.3.6 SS Control Register 2 (SSCR2) ............................................................................ 872
17.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)................................... 873
17.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3).................................... 874
17.3.9 SS Shift Register (SSTRSR)................................................................................. 875
17.4.1 Transfer Clock ...................................................................................................... 876
17.4.2 Relationship of Clock Phase, Polarity, and Data .................................................. 876
17.4.3 Relationship between Data Input/Output Pins and Shift Register ........................ 877
17.4.4 Communication Modes and Pin Functions ........................................................... 879
17.4.5 SSU Mode............................................................................................................. 881
17.4.6 SCS Pin Control and Conflict Error...................................................................... 890
17.4.7 Clock Synchronous Communication Mode .......................................................... 892
17.6.1 Module Standby Mode Setting ............................................................................. 899
17.6.2 Access to SSTDR and SSRDR Registers ............................................................. 899
17.6.3 Continuous Transmission/Reception in SSU Slave Mode.................................... 899