DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 1001

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

18.8
18.8.1
The I
is for I
For details, refer to section 26, Power-Down Modes.
18.8.2
A stop condition or repeated start condition should be issued after the fall of the ninth clock pulse
is recognized. The fall of the ninth clock pulse can be recognized by checking the SCLO bit in the
I
specific timing under the conditions 1 or 2 shown below, the condition may not be output
successfully. Issuance under other than these conditions will succeed with no problem.
1. When the SCL signal did not rise within the time specified in section 18.7, Bit Synchronous
2. When the bit synchronous circuit is activated because the low-level periods of the eighth and
18.8.3
Do not issue a start condition and stop condition in sequence. If a start condition and stop
condition are to be issued in sequence, be sure to transmit a slave address before issuing the stop
condition.
2
C bus control register 2 (ICCR2). When a stop condition or repeated start condition is issued at a
Circuit, due to the load of the SCL bus (load capacitance or pull-up resistor).
ninth clock pulses are extended by the slave device.
2
C2 operation can be disabled or enabled using the standby control register. The initial setting
2
C2 operation to be halted. Access to registers is enabled by clearing module standby mode.
Usage Note
Module Standby Mode Setting
Issuance of Stop Condition and Repeated Start Condition
Issuance of a Start Condition and Stop Condition in Sequence
Rev. 3.00 May 17, 2007 Page 943 of 1582
Section 18 I
2
C Bus Interface 2 (I
REJ09B0181-0300
2
C2)