DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 433

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

The bus release sequence is as follows. The address bus and data bus are placed in a high-
impedance state synchronized with the rising edge of CK. The bus mastership acknowledge signal
is asserted 0.5 cycles after the above high impedance state, synchronized with the falling edge of
CK. The bus control signals such as CSn are placed in the high-impedance state at subsequent
rising edges of CK. These bus control signals go high one cycle before being placed in the high-
impedance state. Bus request signals are sampled at the falling edge of CK. By setting the
HIZCNT bit in CMNR, the CKE, RASU, RASL, CASU, and CASL can be continued to be driven
even after the bus is released using the values immediately before the bus release.
The sequence for reclaiming the bus mastership from an external device is described below.
At 1.5 cycles after the negation of BREQ is detected at the falling edge of CK, the bus control
signals are driven high. The bus acknowledge signal is negated at the next falling edge of the
clock. The fastest timing at which actual bus cycles can be resumed after bus control signal
assertion is at the rising edge of the CK where address and data signals are driven. Figure 9.51
shows the bus arbitration timing in master mode.
In an original external device designed by the user, multiple bus accesses may be generated
continuously to reduce the overhead caused by bus arbitration. In this case, to execute SDRAM
refresh correctly, the external device must be designed to release the bus mastership within the
refresh interval time.
This LSI has the IRQOUT pin to request the bus while waiting for refresh execution. This LSI
continues to assert IRQOUT (low level) until the bus is acquired. When the external device
receives this signal and releases the bus, the LSI acquires the bus and executes refresh.
After BREQ assertion (low level; bus request), the BREQ signal should be negated (high level;
bus release) only after the BACK is asserted (low level; bus acknowledge). If BREQ is negated
before BACK is asserted, BACK may be asserted only for one cycle depending on the BREQ
negation timing, and a bus conflict may occur between the external device and this LSI.
control signals
D31 to D0
A29 to A0
Other bus
BREQ
BACK
CSn
CK
Figure 9.51 Bus Arbitration Timing
Rev. 3.00 May 17, 2007 Page 375 of 1582
Section 9 Bus State Controller (BSC)
REJ09B0181-0300