DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 448

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 10 Direct Memory Access Controller (DMAC)
Rev. 3.00 May 17, 2007 Page 390 of 1582
REJ09B0181-0300
Bit
17
16
15, 14
13, 12
Bit Name
AM
AL
DM[1:0]
SM[1:0]
Initial
Value
0
0
00
00
R/W
R/W
R/W
R/W
R/W
Descriptions
Acknowledge Mode
Selects whether DACK is output in data read cycle or in
data write cycle in dual address mode.
In single address mode, DACK is always output
regardless of the specification by this bit.
0: DACK output in read cycle (dual address mode)
1: DACK output in write cycle (dual address mode)
Acknowledge Level
Specifies whether the DACK signal output is high active
or low active.
0: Low-active output of DACK
1: High-active output of DACK
Destination Address Mode 1, 0
Specify whether the DMA destination address is
incremented, decremented, or left fixed. (In single
address mode, the DM1 and DM0 bits are ignored when
data is transferred to an external device with DACK.)
00: Fixed destination address (setting prohibited in 16-
01: Destination address is incremented (+1 in byte-unit
10: Destination address is decremented (–1 in byte-unit
11: Setting prohibited
Source Address Mode 1, 0
Specify whether the DMA source address is incremented,
decremented, or left fixed. (In single address mode, SM1
and SM0 bits are ignored when data is transferred from
an external device with DACK.)
00: Fixed source address (setting prohibited in 16-byte
01: Source address is incremented (+1 in byte-unit
10: Source address is decremented (–1 in byte-unit
11: Setting prohibited
byte transfer)
transfer, +2 in word-unit transfer, +4 in longword-unit
transfer, +16 in 16-byte transfer)
transfer, –2 in word-unit transfer, –4 in longword-unit
transfer; setting prohibited in 16-byte transfer)
transfer)
transfer, +2 in word-unit transfer, +4 in longword-unit
transfer, +16 in 16-byte transfer)
transfer, –2 in word-unit transfer, –4 in longword-unit
transfer; setting prohibited in 16-byte transfer)