DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 912

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 16 Serial Communication Interface with FIFO (SCIF)
16.7
Note the following when using the SCIF.
16.7.1
The TDFE flag in the serial status register (SCFSR) is set when the number of transmit data bytes
written in the transmit FIFO data register (SCFTDR) has fallen below the transmit trigger number
set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR). After TDFE is set, transmit
data up to the number of empty bytes in SCFTDR can be written, allowing efficient continuous
transmission.
However, if the number of data bytes written in SCFTDR is equal to or less than the transmit
trigger number, the TDFE flag will be set to 1 again after being read as 1 and cleared to 0. TDFE
clearing should therefore be carried out when SCFTDR contains more than the transmit trigger
number of transmit data bytes.
The number of transmit data bytes in SCFTDR can be found from the upper 8 bits of the FIFO
data count register (SCFDR).
16.7.2
The RDF flag in the serial status register (SCFSR) is set when the number of receive data bytes in
the receive FIFO data register (SCFRDR) has become equal to or greater than the receive trigger
number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR). After RDF is set,
receive data equivalent to the trigger number can be read from SCFRDR, allowing efficient
continuous reception.
However, if the number of data bytes in SCFRDR is equal to or greater than the trigger number,
the RDF flag will be set to 1 again if it is cleared to 0. RDF should therefore be cleared to 0 after
being read as 1 after reading the number of the received data in the receive FIFO data register
(SCFRDR) which is less than the trigger number.
The number of receive data bytes in SCFRDR can be found from the lower 8 bits of the FIFO data
count register (SCFDR).
Rev. 3.00 May 17, 2007 Page 854 of 1582
REJ09B0181-0300
Usage Notes
SCFTDR Writing and TDFE Flag
SCFRDR Reading and RDF Flag