DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 1098

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 21 Pin Function Controller (PFC)
21.1.1
PAIORL and PAIORH are 16-bit readable/writable registers that are used to set the pins on port A
as inputs or outputs. Bits PA29IOR to PA0IOR correspond to pins PA29 to PA0 (names of
multiplexed pins are here given as port names and pin numbers alone). PAIORL is enabled when
the port A pins are functioning as general-purpose inputs/outputs (PA15 to PA0). In other states,
PAIORL is disabled. PAIORH is enabled when the port A pins are functioning as general-purpose
input/output (PA29 to PA16). In other states, PAIORH is disabled.
A given pin on port A will be an output pin if the corresponding bit in PAIORH or PAIORL is set
to 1, and an input pin if the bit is cleared to 0.
However, bits 13 to 0 of PAIORH, and bits 11, 6, and 2 to 0 of PAIORL are disabled in SH7083.
Bits 13 to 2 of PAIORH are disabled in SH7084. Bits 13 to 10 of PAIORH are disabled in
SH7085.
Bits 15 and 14 of PAIORH are reserved. These bits are always read as 0. The write value should
always be 0.
The initial values of PAIORL and PAIORH are H'0000, respectively.
• Port A I/O Register H (PAIORH)
Initial value:
• Port A I/O Register L (PAIORL)
Initial value:
Rev. 3.00 May 17, 2007 Page 1040 of 1582
REJ09B0181-0300
R/W:
R/W:
Bit:
Bit:
PA15
R/W
Port A I/O Register L, H (PAIORL, PAIORH)
IOR
15
15
R
0
0
-
PA14
R/W
IOR
14
14
R
0
0
-
PA29
PA13
R/W
R/W
IOR
IOR
13
13
0
0
PA28
R/W
PA12
R/W
IOR
IOR
12
12
0
0
PA27
R/W
PA11
R/W
IOR
IOR
11
11
0
0
PA26
R/W
PA10
R/W
IOR
IOR
10
10
0
0
PA25
R/W
R/W
IOR
PA9
IOR
9
0
9
0
PA24
R/W
R/W
IOR
PA8
IOR
8
0
8
0
PA23
R/W
R/W
IOR
PA7
IOR
7
0
7
0
PA22
R/W
R/W
IOR
PA6
IOR
6
0
6
0
PA21
R/W
R/W
IOR
PA5
IOR
5
0
5
0
R/W
R/W
PA20
IOR
PA4
IOR
4
0
4
0
PA19
R/W
R/W
IOR
PA3
IOR
3
0
3
0
PA18
R/W
R/W
IOR
PA2
IOR
2
0
2
0
R/W
R/W
PA17
IOR
PA1
IOR
1
0
1
0
R/W
R/W
PA16
IOR
PA0
IOR
0
0
0
0