DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 465

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Address Modes:
• Dual Address Mode
In dual address mode, both the transfer source and destination are accessed by an address. The
source and destination can be located externally or internally.
DMA transfer requires two bus cycles because data is read from the transfer source in a data
read cycle and written to the transfer destination in a data write cycle. At this time, transfer
data is temporarily stored in the DMAC. In the transfer between external memories as shown
in figure 10.6, data is read to the DMAC from one external memory in a data read cycle, and
then that data is written to the other external memory in a write cycle.
Auto request, external request, and on-chip peripheral module request are available for the
transfer request. DACK can be output in read cycle or write cycle in dual address mode. The
AM bit in the channel control register (CHCR) can specify whether the DACK is output in
read cycle or write cycle.
The SAR value is an address, data is read from the transfer source module,
and the data is temporarily stored in the DMAC.
The DAR value is an address and the value stored in the data buffer in the
DMAC is written to the transfer destination module.
Data buffer
Data buffer
Figure 10.6 Data Flow of Dual Address Mode
DMAC
DMAC
SAR
DAR
SAR
DAR
Second bus cycle
First bus cycle
Section 10 Direct Memory Access Controller (DMAC)
Transfer destination
Transfer destination
Transfer source
Transfer source
Memory
Memory
module
module
module
module
Rev. 3.00 May 17, 2007 Page 407 of 1582
REJ09B0181-0300