DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 431

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

• When DTC/DMAC activation request is generated during read access to external space from CPU
• When DTC/DMAC activation request is generated during write access to external space from CPU (1)
• When DTC/DMAC activation request is generated during write access to external space from CPU (2)
• When DTC/DMAC activation request is generated during write access to external space from CPU (3)
(When external space read request is generated by CPU during execution of write access to external space from CPU)
(When external space write request is generated by CPU during execution of write access to external space from CPU)
Figure 9.50 Bus Arbitration when DTC or DMAC Activation Request Occurs during
Internal bus
External bus
DTC/DMAC
activation request
Internal bus
External bus
DTC/DMAC
activation request
Internal bus
External bus
DTC/DMAC
activation request
Internal bus
External bus
DTC/DMAC
activation request
DTC/DMAC activation request is generated in this period.
DTC/DMAC activation request is generated in this period.
DTC/DMAC activation request is generated in this period.
space 1 from CPU
Write to external
Write to external
Write to external
space from CPU
space from CPU
DTC/DMAC activation request is generated in this period.
Read access to external
Read access to external
Write access to external
Write access to external
External Space Access from CPU
Write access to external
space from CPU
space from CPU
space from CPU
space from CPU
space 1 from CPU
space 2 from CPU
Write to external
DTC/DMAC
Read access to external
space from CPU
DTC/DMAC
Read access to external
space from CPU
DTC/DMAC
Write access to external
Rev. 3.00 May 17, 2007 Page 373 of 1582
space 2 from CPU
Section 9 Bus State Controller (BSC)
DTC/DMAC
REJ09B0181-0300