DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 940

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 17 Synchronous Serial Communication Unit (SSU)
Rev. 3.00 May 17, 2007 Page 882 of 1582
REJ09B0181-0300
[1]
[2]
[3]
[4]
[5]
[6]
Specify bits MLS, CPOS, CPHS, CKS2,
Set PFC for external pins to be used
Specify bits TE, RE, TEIE, TIE, RIE,
Clear TE and RE bits in SSER to 0
Clear SSUMS in SSCRH to 0 and
Specify bits TENDSTS, SCSATS,
and CEIE in SSER simultaneously
Specify MSS, BIDE, SOL, CSS1,
specify bits DATS1 and DATS0
(SSCK, SSI, SSO, and SCS)
CKS1, and CKS0 in SSMR
and CSS0 bits in SSCRH
Start setting initial values
and SSODTS in SSCR2
End
Figure 17.4 Example of Initial Settings in SSU Mode
[1] Make appropriate settings in the PFC for the external pins to be used.
[2] Specify master/slave mode selection, bidirectional mode enable,
[3] Selects SSU mode and specify transmit/receive data length.
[4] Specify MSB first/LSB first selection, clock polarity selection,
[5] Specify timing of TEND bit setting, SCS pin assertion, and data
[6] Enables/disables interrupt requests to the CPU.
SSO pin output value selection, SSCK pin selection, and SCS pin
selection.
clock phase selection, and transfer clock rate selection.
output on the SSO pin.