DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 1008

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 19 A/D Converter (ADC)
19.3.2
ADCSR for each module controls A/D conversion operations.
Initial value:
Rev. 3.00 May 17, 2007 Page 950 of 1582
REJ09B0181-0300
Bit
15
14
13, 12
11
Note:
R/W:
Bit:
*
Writing 0 to this bit after reading it as 1 is clears the flag and is the only allowed way.
R/(W)* R/W
Bit Name

ADF
ADIE
TRGE
ADF
A/D Control/Status Registers_0 to _2 (ADCSR_0 to ADCSR_2)
15
0
ADIE
14
0
13
Initial
Value
0
0
All 0
0
R
0
-
12
R
0
-
TRGE
R/W
11
0
R/W
R/(W)*
R/W
R
R/W
10
R
0
-
CONADF
R/W
Description
A/D End Flag
A status flag that indicates the end of A/D conversion.
[Setting conditions]
•
•
[Clearing conditions]
•
•
A/D Interrupt Enable
The A/D conversion end interrupt (ADI) request is
enabled when 1 is set
When changing the operating mode, first clear the
ADST bit to 0.
Reserved
These bits are always read as 0. The write value
should always be 0.
Trigger Enable
Enables or disables triggering of A/D conversion by
ADTRG, an MTU2 trigger, or an MTU2S trigger.
0: A/D conversion triggering is disabled
1: A/D conversion triggering is enabled
When changing the operating mode, first clear the
ADST bit to 0.
9
0
When A/D conversion ends in single mode
When A/D conversion ends on all specified
channels in scan mode
When 0 is written after reading ADF = 1
When the DTC or DMAC is activated by an ADI
interrupt and ADDR is read
R/W
STC
8
0
R/W
7
0
CKSL[1:0]
R/W
6
0
R/W
5
0
ADM[1:0]
R/W
4
0
ADCS
R/W
3
0
R/W
2
0
CH[2:0]
R/W
1
0
R/W
0
0