DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 1598

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Rev. 3.00 May 17, 2007 Page 1540 of 1582
REJ09B0181-0300
Item
Figure 1.6 Pin Assignments of
SH7083 (P-LFBGA-112)
Table 1.2 Pin Functions
Figure 3.1 Address Map for Each
Operating Mode in SH7083
(256-Kbyte Flash Memory
Version)
Figure 3.2 Address Map for Each
Operating Mode in SH7083
(512-Kbyte Flash Memory
Version)
Table 4.4 Frequency Division
Ratios Specifiable with FRQCR
Page Revision (See Manual for Details)
12
21,
22
21
58,
59
76
Added
Amended
Deleted
Amended
Amended
Notes: 2. The output frequency of the PLL circuit is the
Classification
User debugging
interface (H-UDI)
(only in the F-ZTAT
version)
E10A interface
(only in the F-ZTAT
version)
Classification
Advanced user
debugger (AUD)
(only in F-ZTAT
version supporting
full functions of
E10A)
7. …….The MTU2 clock (MPφ) frequency must
product of the frequency of the input from the
crystal resonator or EXTAL pin and the
multiplication ratio (×8) of the PLL circuit. This
output frequency must be 80 MHz or lower.
be equal to or lower than the MTU2S clock
(MIφ) frequency and the bus clock (Bφ)
frequency and equal to or higher than the
peripheral clock frequency (Pφ).
Symbol
AUDATA3 to
AUDATA0
AUDRST
AUDMD
Symbol
TCK
ASEMD0
I/O
O
I
I
Name
AUD data
AUD reset
AUD mode Low-level input when the
Function
Test-clock input pin.
Sets the ASE mode.
Function
Branch destination
address output pins.
Reset signal input pin.
AUD function is used.