DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 528

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 3.00 May 17, 2007 Page 470 of 1582
REJ09B0181-0300
Bit
2
1
Bit Name
TGFC
TGFB
Initial
Value
0
0
R/W
R/(W)*
R/(W)*
1
1
Description
Input Capture/Output Compare Flag C
Status flag that indicates the occurrence of TGRC input
capture or compare match in channels 0, 3, and 4. Only
0 can be written, for flag clearing. In channels 1 and 2,
bit 2 is reserved. It is always read as 0 and the write
value should always be 0.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Input Capture/Output Compare Flag B
Status flag that indicates the occurrence of TGRB input
capture or compare match. Only 0 can be written, for
flag clearing.
[Setting conditions]
•
•
[Clearing conditions]
•
•
When TCNT = TGRC and TGRC is functioning as
output compare register
When TCNT value is transferred to TGRC by input
capture signal and TGRC is functioning as input
capture register
When DTC is activated by TGIC interrupt and the
DISEL bit of MRB in DTC is 0
When 0 is written to TGFC after reading TGFC = 1*
When TCNT = TGRB and TGRB is functioning as
output compare register
When TCNT value is transferred to TGRB by input
capture signal and TGRB is functioning as input
capture register
When DTC is activated by TGIB interrupt and the
DISEL bit of MRB in DTC is 0
When 0 is written to TGFB after reading TGFB = 1*
2
2