DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 43

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Figure 28.14 Basic Bus Timing for Normal Space
Figure 28.15 CS Extended Bus Cycle for Normal Space
Figure 28.16 Bus Cycle of SRAM with Byte Selection
Figure 28.17 Bus Cycle of SRAM with Byte Selection
Figure 28.18 MPX-I/O Interface Bus Cycle
Figure 28.19 Burst MPX-I/O Interface Bus Cycle Single Read Write
Figure 28.20 Burst MPX-I/O Interface Bus Cycle Single Read Write
Figure 28.21 Burst MPX-I/O Interface Bus Cycle Burst Read Write
Figure 28.22 Burst MPX-I/O Interface Bus Cycle Burst Read Write
Figure 28.23 Burst ROM Read Cycle
Figure 28.24 Synchronous DRAM Single Read Bus Cycle
Figure 28.25 Synchronous DRAM Single Read Bus Cycle
Figure 28.26 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
Figure 28.27 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
Figure 28.28 Synchronous DRAM Single Write Bus Cycle
Figure 28.29 Synchronous DRAM Single Write Bus Cycle
Figure 28.30 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
Figure 28.31 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
(One Software Wait Cycle, External Wait Cycle Valid (WM Bit = 0),
No Idle Cycle) ..................................................................................................... 1424
(SW = 1 Cycle, HW = 1 Cycle, One External Wait Cycle)................................. 1425
(SW = 1 Cycle, HW = 1 Cycle, One External Wait Cycle, BAS = 0
(UB/LB in Write Cycle Controlled))................................................................... 1426
(SW = 1 Cycle, HW = 1 Cycle, One External Wait Cycle, BAS = 1
(WE in Write Cycle Controlled)) ........................................................................ 1427
(Three Address Cycles, One Software Wait Cycle, One External Wait Cycle) .. 1428
(One Address Cycle, One Software Wait Cycle) ................................................ 1429
(One Address Cycle, One Software Wait Cycle, One External Wait Cycle) ...... 1430
(One Address Cycle, One Software Wait Cycle) ................................................ 1431
(One Address Cycle, One Software Wait Cycle, External Wait Cycle) .............. 1432
(One Software Wait Cycle, One External Wait Cycle, One Burst Wait Cycle,
Two Bursts) ......................................................................................................... 1433
(Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 0 Cycle)......... 1434
(Auto Precharge, CAS Latency 2, WTRCD = 1 Cycle, WTRP = 1 Cycle)......... 1435
(Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 1 Cycle)......... 1436
(Auto Precharge, CAS Latency 2, WTRCD = 1 Cycle, WTRP = 0 Cycle)......... 1437
(Auto Precharge, WTRCD = 2 Cycles, TRWL = 1 Cycle) ................................. 1439
(Auto Precharge, WTRCD = 0 Cycle, TRWL = 1 Cycle)................................... 1440
(Auto Precharge, WTRCD = 1 Cycle, TRWL = 1 Cycle)................................... 1441
(Auto Precharge, TRWL = 1 Cycle)................................................................... 1438
Rev. 3.00 May 17, 2007 Page xliii of Iviii