DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 1334

IC SUPERH MCU FLASH 112LQFP

DF70845AD80FPV

Manufacturer Part Number
DF70845AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet

Specifications of DF70845AD80FPV

Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
32KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF70845AD80FPV
Manufacturer:
TAIYO
Quantity:
40 000
Part Number:
DF70845AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 23 Flash Memory
1. After the data to be programmed has fixed values, clear the RAMS bit to 0 to cancel the
2. Transfer the user programming/erasing procedure program to RAM.
3. Run the programming/erasing procedure program in RAM and download the on-chip
4. When the EB0 area of the user MAT has not been erased, erasing must be performed before
Note: Setting the RAMS bit to 1 puts all the blocks in flash memory in the
Rev. 3.00 May 17, 2007 Page 1276 of 1582
REJ09B0181-0300
Figure 23.19 Programming of Tuned Data (SH7083: 256-kbyte Flash Memory Version)
overlap of RAM. Emulation mode is canceled and emulation protection is also cleared.
programming/erasing program.
Specify the download start address with FTDAR so that the tuned data area does not overlap
with the download area.
programming. Set the parameters FMPAR and FMPDR so that the tuned data is designated,
and execute programming.
programming/erasing-protected state regardless of the values of the RAM2 to RAM0 bits
(emulation protection). Clear the RAMS bit to 0 before actual programming or erasure.
Though RAM emulation can also be carried out with the user boot MAT selected, the user
boot MAT can be erased or programmed only in boot mode or programmer mode.
H'3FFFF
H'00000
H'01000
H'02000
H'03000
H'04000
H'05000
H'06000
H'07000
H'08000
Flash memory
EB8 to EB11
(user MAT)
EB0
EB1
EB2
EB3
EB4
EB5
EB6
EB7
(1) Cancel the emulation mode.
(2) Transfer the user programming/erasing
(3) Download the on-chip programming/
(4) Execute programming after erasing.
procedure program.
erasing program to the destination set
by FTDAR without overlapping the tuned
data area.
Programming/erasing
procedure program
<On-chip RAM>
Tuned data area
Download area
area
H'FFFFA000
H'FFFFAFFF
FTDAR setting
H'FFFFBFFF

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