DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 819

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in the serial status register (SCSSR). If it is cleared to 0, the
2. After transferring data from SCTDR to SCTSR, the SCI sets the TDRE flag to 1 and starts
3. The SCI checks the TDRE flag at the timing for sending the stop bit.
SCI recognizes that data has been written to the transmit data register (SCTDR) and transfers
the data from SCTDR to the transmit shift register (SCTSR).
transmission. If the TIE bit in the serial control register (SCSCR) is set to 1 at this time, a
transmit-data-empty interrupt (TXI) request is generated.
The serial transmit data is sent from the TXD pin in the following order.
A. Start bit: One-bit 0 is output.
B. Transmit data: 8-bit or 7-bit data is output in LSB-first order.
C. Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor
D. Stop bit(s): One or two 1 bits (stop bits) are output.
E. Mark state: 1 is output continuously until the start bit that starts the next transmission is
If the TDRE flag is 0, the data is transferred from SCTDR to SCTSR, the stop bit is sent, and
then serial transmission of the next frame is started.
If the TDRE flag is 1, the TEND flag in SCSSR is set to 1, the stop bit is sent, and then the
"mark state" is entered in which 1 is output. If the TEIE bit in SCSCR is set to 1 at this time, a
TEI interrupt request is generated.
bit is output. (A format in which neither parity nor multiprocessor bit is output can also be
selected.)
sent.
Section 15 Serial Communication Interface (SCI)
Rev. 3.00 May 17, 2007 Page 761 of 1582
REJ09B0181-0300