MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 83
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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2.6.1
Table 2-7
Freescale Semiconductor
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ASL
ASR
Bcc
Instruction
Instruction
Address
MSW
LSW
MSB
LSB
msb
Bit
lsb
d
{}
()
C
N
V
X
Z
n
lists implemented user-mode instructions by opcode.
Instruction Set Summary
Dy,<ea>x
<ea>y,Dx
<ea>y,Ax
#<data>,Dx
#<data>,<ea>x
Dy,Dx
Dy,<ea>x
<ea>y,Dx
#<data>,Dx
Dy,Dx
#<data>,Dx
Dy,Dx
#<data>,Dx
<label>
Operand Syntax
Optional operation
Identifies an indirect address
Displacement value, n-bits wide (example: d
Calculated effective address (pointer)
Bit selection (example: Bit 3 of D0)
Least significant bit (example: lsb of D0)
Least significant byte
Least significant word
Most significant bit
Most significant byte
Most significant word
Carry
Negative
Overflow
Extend
Zero
MCF5272 ColdFire
Table 2-7. User-Mode Instruction Set Summary
Table 2-6. Notational Conventions (continued)
.L
.L
.L
.L
.L
.L
.L
.L
.L
.L
.L
.L
.L
.B,.W
Operand Size
Condition Code Register Bit Names
®
Integrated Microprocessor User’s Manual, Rev. 3
Subfields and Qualifiers
Source + destination → destination
Source + destination → destination
Immediate data + destination → destination
Immediate data + destination → destination
Source + destination + X → destination
Source & destination → destination
Immediate data & destination → destination
X/C ← (Dx << Dy) ← 0
X/C ← (Dx << #<data>) ← 0
MSB → (Dx >> Dy) → X/C
MSB → (Dx >> #<data>) → X/C
If condition true, then PC + 2 + d
Operand Syntax
16
is a 16-bit displacement)
Operation
n
→ PC
ColdFire Core
2-15
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