MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 356

• Manufacturer Part Number: MCF5272CVF66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Leaded Process Compatible: No
• Rohs Compliant: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No

Timer Module
Timers 0 and 1 may output a signal on the timer outputs (TOUT0 or TOUT1) when the reference value is
reached, as selected by the output mode bit, TMR[OM]. This signal can be an active-low pulse or a toggle
of the current output, under program control.
The TCAPs are used to latch counter values when the corresponding input capture edge detector detects a
defined transition (of TIN0, TIN1, URT0_RxD, or URT1_RxD). The type of transition triggering the
capture is selected by the capture edge bits, TMR[CE].A capture or reference event sets the TER bit and
generates a maskable interrupt.
15-2
15
15
15
15
15
15
15
15
15
15
Timer Reference Register (TRR0)
Timer Reference Register (TRR2)
Timer Capture Register (TCAP0)
Timer Capture Register (TCAP2)
Prescaler
Prescaler
Timer Mode Register (TMR0)
Timer Mode Register (TMR 2)
Timer Event Register (TER0)
Timer Event Register (TER2)
Divider
Divider
Timer Counter (TCN0)
Timer Counter (TCN2)
MCF5272 ColdFire
Timer 0
Timer 2
Timer 1
Timer 3
Mode Bits
Mode Bits
Clock
Clock
Figure 15-1. Timer Block Diagram
®
0
0
0
0
0
0
0
0
0
0
Integrated Microprocessor User’s Manual, Rev. 3
Data [16)
Generator
Generator
Detection
Detection
Capture
Capture
Timer
Clock
Timer
Clock
TOUT1
TOUT0
Interrupt (T1)
Interrupt (T0)
System Clock or
System Clock/16
UART1_RxD
UART0_RxD
Interrupt (T3)
Interrupt (T2)
System Clock or
System Clock/16
TIN1
TIN0
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