MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 214
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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DMA Controller
10.2
The DMA address mode determines how the address output by the channel is updated after a transfer to
be ready for the next transfer. The two following modes are supported:
10.3
The MCF5272 DMA controller supports a single DMA channel which can be used for
memory-to-memory transfers.
10.3.1
The DMR controls various operation modes, principally the request and addressing modes. Fields include
the transfer size and modifier, transfer direction, channel enable and reset.
Table 10-2
10-2
29–20
Bits
31
30
•
•
Reset
Reset
Field RESET
Field
Addr
R/W
R/W
Static address mode—The address remains unchanged after the transfer completes. This mode
should be used when the source or destination address is the FIFO data port of an on-chip
peripheral.
Increment address mode—In increment address mode, the address is incremented at the end of the
transfer by the number of bytes transferred. This mode should be used when a source or destination
address is in external memory.
RESET Reset. Writing a 1 to this location causes the DMA controller to reset to a condition where no transfers are
Name
DMA Address Modes
DMA Controller Registers
EN
—
describes DMR fields.
DMA Mode Register (DMR)
—
31
15
0
taking place. EN is cleared, preventing new transfers.
Enable. Controls whether the DMA channel is enabled to perform transfers.
0 DMA transfers are disabled.
1 DMA transfers are enabled. The DMA controller can respond to requests from the peripheral or generates
Reserved, should be cleared.
internal requests in dual address mode, so long as the conditions described under the DMA interrupt
flags (see
EN
30
14
DSTM
MCF5272 ColdFire
01
29
13
Section 10.3.2, “DMA Interrupt Register
12
DSTT
Figure 10-1. DMA Mode Register (DMR)
1_00
Table 10-2. DMR Field Descriptions
®
10
Integrated Microprocessor User’s Manual, Rev. 3
9
DSTS
0000_0000_0000_0000
01
MBAR + 0x00E0
8
—
R/W
R/W
Description
—
0
7
(DIR)”) do not prevent transfers from going ahead.
—
0
6
SRCM
1
5
20
4
SRCT
1_01
19
RQM
Freescale Semiconductor
18
2
17
1
SRCS
—
01
16
0
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