MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 300

• Manufacturer Part Number: MCF5272CVF66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Leaded Process Compatible: No
• Rohs Compliant: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No

Physical Layer Interface Controller (PLIC)
Figure 13-3
receive channel.
After reset, the B- and D-channel shift registers and shadow registers are initialized to all ones.
13.2.2
The maximum transmission rate for each GCI/IDL port is 144 Kbps: the sum of two 64-Kbps B channels
and one 16-Kbps D-channel. Frames of B
receive side.
Because the reception and transmission of information on the GCI/IDL interface is deterministic, a
common interrupt is generated at the 2-KHz rate. It is expected that a common interrupt service routine
services the transmit and receive registers.
After reset, the B- and D-channel shift registers and shadow registers are initialized to all ones.
13-4
B1, B2, Receive
Data Register
DCL
Shadow Register
Dout
GCI/IDL B- and D-Channel Transmit Data Registers
shows the shift register, shadow register, internal bus register, and multiplexor for each B
DIN
64 Kbps
Figure 13-3. GCI/IDL B-Channel Receive Data Register Demultiplexing
B1 Shift Register
MCF5272 ColdFire
START
B1
32
8 bits
Figure 13-4. GCI/IDL Transmit Data Flow
®
Integrated Microprocessor User’s Manual, Rev. 3
1
B2 Shift Register
, B
Internal Bus
8 bits
2
, and D-channels are packed together in a similar way to the
Shift Register (B1 or B2)
B2
DEMUX
32 bits
32
8 bits
32
32
8 bits
D Shift Register
2-KHz transfer and interrupt
8-KHz Rate
8 bits
D
8
Internal Bus
END
Multiplexing
Circuitry
Freescale Semiconductor