MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 228
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Ethernet Module
11.5
This section gives an overview of the registers, followed by a description of the buffers.
The FEC is programmed by a combination of control/status registers (CSRs) and buffer descriptors. The
CSRs are used for mode control and to extract global status information. The descriptors are used to pass
data buffers and related buffer information between the hardware and software.
Table 11-6
The following sections describe each register in detail.
11-10
Programming Model
shows the FEC register memory map with each register address, name, and a brief description.
0xC40–
0x8CC
0xC0C
Offset
0x84C
0x8D0
0x8EC
0xC00
0xC04
0xC08
0xC10
0xC14
0xC18
0xDFF
0x8E4
0x840
0x844
0x848
0x850
0x854
0x880
0x884
0x944
0x948
0x984
MCF5272 ColdFire
ECR
EIR
EIMR
IVSR
RDAR
TDAR
MMFR
MSCR
FRBR
FRSR
TFSR
TFWR
RCR
MFLR
TCR
MALR
MAUR
HTUR
HTLR
ERDSR
ETDSR
EMRBR
EFIFO
Name
Table 11-6. FEC Register Memory Map
®
Integrated Microprocessor User’s Manual, Rev. 3
Width
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Ethernet control
Interrupt event
Interrupt mask
Interrupt vector status
Receive descriptor active
Transmit descriptor active
MII management frame
MII speed control
FIFO receive bound
FIFO receive start
FIFO transmit start
Transmit FIFO
Receive control
Maximum frame length
Transmit control
Lower 32-bits of MAC address
Upper 16-bits of MAC address
Upper 32-bits of hash
Lower 32-bits of hash
Pointer to receive descriptor
Pointer to transmit descriptor
Maximum receive buffer
FIFO RAM space
watermark, [p. 11-21]
register, [p. 11-12]
register, [p. 11-13]
register, [p. 11-23]
register, [p. 11-11]
register, [p. 11-25]
Description
register, [p. 11-18]
register, [p. 11-20]
register, [p. 11-22]
register, [p. 11-19]
table, [p. 11-29]
table, [p. 11-28]
register, [p. 11-14]
register, [p. 11-24]
register, [p. 11-17]
size, [p. 11-32]
register, [p. 11-15]
register, [p. 11-16]
ring, [p. 11-30]
ring, [p. 11-31]
Freescale Semiconductor
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