MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 372

• Manufacturer Part Number: MCF5272CVF66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Leaded Process Compatible: No
• Rohs Compliant: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No

UART Modules
16.3.9
The UART auxiliary control registers (UACRn),
control based on the receiver FIFO level.
Table 16-8
16.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn)
The UART interrupt status registers (UISRn),
sources. UISRn contents are masked by UIMRn. If corresponding UISRn and UIMRn bits are set, the
internal interrupt output is asserted. If a UIMRn bit is cleared, the state of the corresponding UISRn bit has
no effect on the output.
16-12
Bits
7–3
2–1
0
Address
Reset
Field
Name
RTSL
R/W
IEC
—
describes UACRn fields.
UART Auxiliary Control Registers (UACRn)
Reserved, should be cleared.
RTS level. Determines when RTS is negated by the receiver relative to the fullness of the receiver FIFO. Note
that RTS must first be manually asserted by a write to UOP0n.
00 FIFO level control disabled
01 Receiver FIFO Š 25% full
10 Receiver FIFO Š 50% full
11 Receiver FIFO Š 75% full
Receiver overrun can be prevented by using the RTS output to control the CTS input of the transmitting device.
Attempting to program a receiver and transmitter in the same channel for RTS control is not permitted and
disables RTS control for both.
Input enable control.
0 Setting the corresponding UIPCRn bit has no effect on UISRn[COS].
1 UISRn[COS] is set and an interrupt is generated when the UIPCRn[COS] is set by an external transition on
True status is provided in the UISRn regardless of UIMRn settings. UISRn
is cleared when the UART module is reset.
the CTS input (if UIMRn[COS] = 1).
7
MCF5272 ColdFire
Figure 16-10. UART Auxiliary Control Registers (UACRn)
Table 16-8. UACRn Field Descriptions
®
—
MBAR + 0x110 (UACR0), 0x150 (UACR1)
Integrated Microprocessor User’s Manual, Rev. 3
Figure
Figure
NOTE
0000_0000
Write only
16-11, provide status for all potential interrupt
Description
16-10, control the input enable as well as the RTS
3
2
RTSL
Freescale Semiconductor
1
IEC
0