MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 167
MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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6.2.5
The power management register (PMR),
including low-power sleep, low-power stop, and powering down individual on-chip modules.
Table 6-5
Freescale Semiconductor
11, 3
10, 2
Bits
9, 1
8, 0
Address
HWTEN
RPVEN
EXTEN
SUVEN
Fields
Reset
Reset
Reset
Reset
HWT,
RPV,
SUV,
describes PMR fields.
EXT,
Field BDMPDN
Field DMAPDN PWMPDN QSPIPDN TIMERPDN GPIOPDN USBPDN UART1PDN UART0PDN
Field
Field
R/W
R/W
R/W
R/W
Power Management Register (PMR)
Hardware watchdog timeout. This bit is set when the hardware watchdog timer has reached its
programmed timeout value. If HWTEN is also set, the bus cycle is terminated with an access error
exception.
Read protect violation. This bit is set when a read access is attempted to an area for which the chip select
is set to write only. If RPVEN is also set, the bus cycle is terminated with an access error exception.
External transfer error. This bit is set when an external transfer error is reported to the SIM on TEA. If
EXTEN is also set, the bus cycle is terminated with an access error exception.
Supervisor/user violation. This bit is set when a user mode access is attempted to an area for which the
chip select is set to supervisor only. If SUVEN is also set, the bus cycle is terminated with an access error
exception.
31
23
15
7
MCF5272 ColdFire
—
30
22
6
Figure 6-5. Power Management Register (PMR)
Table 6-4. SPR Field Descriptions (continued)
MOS
®
21
5
—
Integrated Microprocessor User’s Manual, Rev. 3
Figure
—
R/W, Supervisor mode only
R/W, Supervisor mode only
R/W, Supervisor mode only
R/W, Supervisor mode only
SLPEN
6-5, is used to control the various low-power options
20
4
MBAR+0x008
0000_0000
0000_0000
0000_0000
0000_0000
Description
27
19
11
3
ENETPDN
USBWK
26
18
10
—
UART1WK
PLIPDN
System Integration Module (SIM)
25
17
9
DRAMPDN
UART0WK
24
16
8
0
6-7
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