MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 387
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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16.5.3.1
In automatic echo mode, shown in
The local CPU-to-receiver communication continues normally, but the CPU-to-transmitter link is
disabled. In this mode, received data is clocked on the receiver clock and resent on TxD. The receiver must
be enabled, but the transmitter need not be.
Because the transmitter is inactive, USRn[TxEMP,TxRDY] are inactive and data is sent as it is received.
Received parity is checked but is not recalculated for transmission. Character framing is also checked, but
stop bits are sent as they are received. A received break is echoed as received until the next valid start bit
is detected. Autobaud operation does not affect automatic echo mode; that is, the first character received
is correctly echoed back.
16.5.3.2
Figure 16-28
testing the operation of a local UART module channel by sending data to the transmitter and checking data
assembled by the receiver to ensure proper operations.
Features of this local loop-back mode are as follows:
16.5.3.3
In remote loop-back mode, shown in
by bit on the TxD output. The local CPU-to-transmitter link is disabled. This mode is useful in testing
receiver and transmitter operation of a remote channel. For this mode, the transmitter uses the receiver
clock.
Freescale Semiconductor
•
•
•
•
Transmitter and CPU-to-receiver communications continue normally in this mode.
RxD input data is ignored
TxD is held marking
The receiver is clocked by the transmitter clock. The transmitter must be enabled, but the receiver
need not be.
Automatic Echo Mode
Local Loop-Back Mode
shows how TxD and RxD are internally connected in local loop-back mode. This mode is for
Remote Loop-Back Mode
MCF5272 ColdFire
CPU
CPU
Disabled
Figure
Figure 16-28. Local Loop-Back
Figure
Figure 16-27. Automatic Echo
®
Integrated Microprocessor User’s Manual, Rev. 3
16-27, the UART automatically resends received data bit by bit.
16-29, the channel automatically transmits received data bit
Rx
Tx
Rx
Tx
Disabled
Disabled
Disabled
RxD Input
TxD Input
RxD Input
TxD Input
UART Modules
16-27
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