MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 320
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Physical Layer Interface Controller (PLIC)
13.5.12 GCI Monitor Channel Receive Registers (P0GMR–P3GMR)
All bits in these registers are read only and are initialized to 0x00FF on hardware or software reset.
PnGMR are 16-bit registers containing the received monitor channel bits for each of the four receive ports
on the MCF5272.
A byte of monitor channel data received on a certain port is put into an associated register using the format
shown in
registers.
13-24
15–11
Bits
7–0
10
Reset
9
8
Field
Addr
R/W
Figure
15
Name
EOM
MC
AB
—
M
13-24. A maskable interrupt is generated when a byte is written into any of these four
Figure 13-24. GCI Monitor Channel Receive Registers (P0GMR–P3GMR)
Reserved, should be cleared.
End of message.
0 Default at reset.
1 Indicates to the CPU that an end-of-message condition has been recognized on the E bit. EOM is
Abort.
0 Default at reset.
1 Indicates that the GCI controller has recognized an abort condition and is acknowledging the abort.
Monitor change.
0 Default at reset.
1 Indicates to the CPU that the monitor channel data byte written to the respective PnGMR register
Monitor channel data byte.
MCF5272 ColdFire
—
MBAR + 0x360 (P0GMR); 0x362 (P1GMR); 0x364 (P2GMR); 0x366 (P3GMR)
automatically cleared when the PnGMR register has been read by the CPU.
It is automatically cleared by the CPU when the PnGMR register has been read.
has changed and that the data is available for processing. Automatically cleared by the CPU when
the PnGMR register has been read. Clearing this bit by reading this register also clears the
aperiodic GMR interrupt.
Table 13-7. P0GMR–P3GMR Field Descriptions
11
®
EOM
Integrated Microprocessor User’s Manual, Rev. 3
10
AB
0000_0000_1111_1111
9
Read Only
MC
8
Description
7
M
Freescale Semiconductor
0
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