MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 429

• Manufacturer Part Number: MCF5272CVF66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Leaded Process Compatible: No
• Rohs Compliant: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No

19.3
The 23 dedicated address signals, A[22:0], define the address of external byte, word, and longword
accesses. These three-state outputs are the 23 lsbs of the internal 32-bit address bus and are multiplexed
with the SDRAM controller row and column addresses (SDA[13:0]).
Fourteen address signals are used for connecting to SDRAM devices as large as 256 Mbits.
The MCF5272 supports SDRAM widths of 16 or 32 bits. For a 32-bit width, SDRAM address signals are
multiplexed starting with A2. For a 16-bit width, address signals are multiplexed starting with A1.
19.4
The 32-bit, three-state, bidirectional, non-multiplexed data bus transfers data to and from the MCF5272.
A read or write operation can transfer 8, 16, or 32 bits in one bus cycle. When a 16-bit data bus is used,
mode parallel port C pins can be multiplexed onto D[15:0].
Data read from or written to on-chip peripherals is visible on the external data bus when the device’s
external bus width is 32 bits. When the device is configured for external 16-bit wide data bus and the data
access is 32 bits wide, the lower 16 bits of on-chip data are not visible externally. On-chip cache, ROM,
and SRAM accesses are not visible externally.
19.4.1
When the device is in normal mode, dynamic bus sizing lets the programmer change data bus width
between 8, 32, and 16 bits for each chip select. The initial width for the bootstrap program chip select, CS0,
is determined by the state of BUSW[1:0]. The program should select bus widths for the other chip selects
before accessing the associated memory space.
19.5
The eight chip selects, CS[7:0], allow the MCF5272 to interface directly to SRAM, EPROM, EEPROM,
and external memory-mapped peripherals. These signals can be programmed for an address location, with
masking capabilities, port size, burst capability indication, and wait-state generation.
CS0 provides a special function as a global chip select that allows access to boot ROM at reset. CS0 can
have its address redefined after reset. CS0 is the only chip select initialized and enabled during reset. All
other chip selects are disabled at reset and must be initialized by device initialization software.
CS7/SDCS can be configured to access RAM or ROM or one physical bank of SDRAM. Only CS7 can
be used for SDRAM chip select.
Freescale Semiconductor
Address Bus (A[22:0]/SDA[13:0])
Data Bus (D[31:0])
Chip Selects (CS7/SDCS, CS[6:0])
Dynamic Data Bus Sizing
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
Signal Descriptions
19-19