MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 16

• Manufacturer Part Number: MCF5272CVF66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Leaded Process Compatible: No
• Rohs Compliant: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No

Paragraph
Number
5.5 Background Debug Mode (BDM) ............................................................................................... 5-15
5.6 Real-Time Debug Support ........................................................................................................... 5-33
5.7 Processor Status, DDATA Definition ........................................................................................... 5-36
5.8 Freescale-Recommended BDM Pinout ....................................................................................... 5-41
6.1 Features .......................................................................................................................................... 6-1
6.2 Programming Model ...................................................................................................................... 6-2
xvi
5.4.5 Data Breakpoint/Mask Registers (DBR, DBMR) ............................................................ 5-12
5.4.6 Program Counter Breakpoint/Mask Registers
5.4.7 Trigger Definition Register (TDR) ................................................................................... 5-14
5.5.1 CPU Halt .......................................................................................................................... 5-16
5.5.2 BDM Serial Interface ....................................................................................................... 5-17
5.5.3 BDM Command Set ......................................................................................................... 5-19
5.6.1 Theory of Operation .......................................................................................................... 5-34
5.6.2 Concurrent BDM and Processor Operation ...................................................................... 5-35
5.7.1 User Instruction Set .......................................................................................................... 5-36
5.7.2 Supervisor Instruction Set ................................................................................................ 5-40
6.2.1 SIM Register Memory Map ................................................................................................ 6-2
6.2.2 Module Base Address Register (MBAR) ........................................................................... 6-3
(PBR, PBMR) ............................................................................................................................ 5-13
5.5.2.1 Receive Packet Format ....................................................................................... 5-18
5.5.2.2 Transmit Packet Format ...................................................................................... 5-18
5.5.3.1 ColdFire BDM Command Format ...................................................................... 5-20
5.5.3.2 Command Sequence Diagrams ........................................................................... 5-21
5.5.3.3 Command Set Descriptions ................................................................................ 5-22
5.6.1.1 Emulator Mode ................................................................................................... 5-35
5.5.3.1.1 Extension Words as Required .................................................................... 5-20
5.5.3.3.1 Read A/D Register (
5.5.3.3.2 Write A/D Register (
5.5.3.3.3 Read Memory Location (
5.5.3.3.4 Write Memory Location (
5.5.3.3.5 Dump Memory Block (
5.5.3.3.6 Fill Memory Block (
5.5.3.3.7 Resume Execution (
5.5.3.3.8 No Operation (
5.5.3.3.9 Read Control Register (
5.5.3.3.10 Write Control Register (
5.5.3.3.11 Read Debug Module Register (
5.5.3.3.12 Write Debug Module Register (
MCF5272 ColdFire
Table of Contents (Continued)
System Integration Module (SIM)
®
Integrated Microprocessor User’s Manual, Rev. 3
NOP
Chapter 6
).................................................................................... 5-30
GO
RAREG
FILL
WAREG
Title
) ............................................................................. 5-29
DUMP
RCREG
) .......................................................................... 5-28
READ
WCREG
WRITE
/
RDREG
/
WDREG
) ................................................................... 5-27
).................................................................. 5-30
) ................................................................. 5-24
)............................................................... 5-25
RDMREG
).............................................................. 5-31
WDMREG
)........................................................... 5-22
) ........................................................ 5-23
)................................................. 5-32
)............................................... 5-33
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