MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 210

• Manufacturer Part Number: MCF5272CVF66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Leaded Process Compatible: No
• Rohs Compliant: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No

SDRAM Controller
9.10.3
Figure 9-13
SDRAM writes all of its on-chip RAM page buffers into the SDRAM array. SDTR[RP] determines the
number of dead cycles after a precharge. Note that self refresh occurs during T3. In refresh state, SDRAM
cannot accept any other command.
9-20
A10_PRECHG
SDADR[13:0]
SDBA[1:0]
SDCLKE
SDCLK
SDWE
SDCS
SDRAM Refresh Timing
RAS0
CAS0
shows refresh-cycle timing. As in
(H)
MCF5272 ColdFire
T0
Precharge
All Banks
T1
Figure 9-13. SDRAM Refresh Cycle
®
T2
Integrated Microprocessor User’s Manual, Rev. 3
NOP
Figure
T3
Refresh
Auto
9-14, during a
T4
T5
PRECHARGE ALL
T6
t
RC
T7
Freescale Semiconductor
command (T1), the
Next Command
T8
T9