MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 70
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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ColdFire Core
2.1.1.1
The IFP generates instruction addresses and fetches. Because the fetch and execution pipelines are
decoupled by a three longword FIFO buffer, the IFP can prefetch instructions before the OEP needs them,
minimizing stalls.
2.1.1.2
The OEP is a two-stage pipeline featuring a traditional RISC datapath with a register file feeding an
arithmetic/logic unit (ALU). For simple register-to-register instructions, the first stage of the OEP
performs the instruction decode and fetching of the required register operands (OC), while the actual
instruction execution is performed in the second stage (EX).
For memory-to-register instructions, the instruction is effectively staged through the OEP twice in the
following way:
2-2
•
•
•
•
The instruction is decoded and the components of the operand address are selected (DS).
The operand address is generated using the execute engine (AG).
The memory operand is fetched while any register operand is simultaneously fetched (OC).
The instruction is executed (EX).
Instruction Fetch Pipeline (IFP)
Operand Execution Pipeline (OEP)
Instruction
Fetch
Pipeline
Operand
Execution
Pipeline
MCF5272 ColdFire
DSOC
AGEX
IAG
IC
IB
Decode & Select,
Instruction Buffer
Operand Fetch
Generation,
Fetch Cycle
Instruction
Generation
Instruction
®
Figure 2-1. ColdFire Pipeline
Address
Address
Execute
Integrated Microprocessor User’s Manual, Rev. 3
FIFO
Address [31:0]
Data[31:0]
Freescale Semiconductor
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