MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 475
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 21
IEEE 1149.1 Test Access Port (JTAG)
This chapter describes the dedicated user-accessible test logic implemented on the MCF5272. This test
logic complies fully with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture.
This chapter describes those items required by the standard and provides additional information specific
to the MCF5272 implementation. For internal details and sample applications, see the IEEE 1149.1
document.
21.1
Problems with testing high-density circuit boards led to development of this standard under the
sponsorship of the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The
MCF5272 supports circuit board test strategies based on this standard.
The test logic includes a test access port (TAP) consisting a 16-state controller, an instruction register, and
three test registers (a 1-bit bypass register, a 265-bit boundary-scan register, and a 32-bit ID register). The
boundary scan register links the device’s pins into one shift register. The contents of this register can be
found at the ColdFire website at http://www.freescale.com. Test logic, implemented using static logic
design, is independent of the device system logic. The TAP includes the following dedicated signals:
These signals, described in detail in
(MTMOD).
The MCF5272 implementation can do the following:
Freescale Semiconductor
•
•
•
•
•
•
•
•
•
TCK—Test clock input to synchronize the test logic.
TMS—Test mode select input (with an internal pullup resistor) that is sampled on the rising edge
of TCK to sequence the TAP controller's state machine.
TDI—Test data input (with an internal pull-up resistor) that is sampled on the rising edge of TCK.
TDO—three-state test data output that is actively driven in the shift-IR and shift-DR controller
states. TDO changes on the falling edge of TCK.
Perform boundary scan operations to test circuit board electrical continuity
Sample MCF5272 system pins during operation and transparently shift out the result in the
boundary scan register
Bypass the MCF5272 for a given circuit board test by effectively reducing the boundary-scan
register to a single bit
Disable the output drive to pins during circuit-board testing
Drive output pins to stable levels
Overview
MCF5272 ColdFire
Table
®
Integrated Microprocessor User’s Manual, Rev. 3
21-1, are enabled by negating the Freescale test mode signal
21-1
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