MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 130
MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Debug Support
5.4.5
The data breakpoint register (DBR),
mode. DBR bits are masked by setting corresponding DBMR bits, as defined in TDR.
Table 5-9
Table 5-10
The DBR supports both aligned and misaligned references.
processor address, access size, and location within the 32-bit data bus.
5-12
31–0
31–0
Bits
Bits
DRc[4–0]
Reset
Field
R/W DBR is accessible in supervisor mode as debug control register 0x0E, using the WDEBUG instruction and
Name
Name
Data
Mask
describes DBR fields.
describes DBMR fields.
Data Breakpoint/Mask Registers (DBR, DBMR)
through the BDM port using the
DBMR is accessible in supervisor mode as debug control register 0x0F,using the WDEBUG instruction and
via the BDM port using the
31
Data breakpoint value. Contains the value to be compared with the data value from the processor’s local bus
as a breakpoint trigger.
Data breakpoint mask. The 32-bit mask for the data breakpoint trigger. Clearing a DBR bit allows the
corresponding DBR bit to be compared to the appropriate bit of the processor’s local data bus. Setting a
DBMR bit causes that bit to be ignored.
MCF5272 ColdFire
Figure 5-8. Data Breakpoint/Mask Registers (DBR and DBMR)
Table 5-11. Access Size and Operand Data Location
A[1:0]
00
01
10
11
0x
1x
xx
Table 5-10. DBMR Field Descriptions
WDMREG
Table 5-9. DBR Field Descriptions
Figure
®
RDMREG
Integrated Microprocessor User’s Manual, Rev. 3
command.
5-8, specify data patterns used as part of the trigger into debug
Access Size
Data (DBR); Mask (DBMR)
0x0E (DBR), 0x0F (DBMR)
and
Longword
Word
Word
Byte
Byte
Byte
Byte
WDMREG
Uninitialized
Description
Description
commands.
Table 5-11
Operand Location
D[31:24]
D[23:16]
D[31:16]
D[15:8]
D[15:0]
D[31:0]
D[7:0]
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