MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 362
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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UART Modules
16.2
The MCF5272 contains two independent UART modules, whose features are as follows:
The MCF5272 UART modules are identical to those on other ColdFire devices, such as the MCF5206e,
with the following exceptions:
16.3
This section contains a detailed description of each register and its specific function. Flowcharts in
Section 16.5.6,
module is controlled by writing control bytes into the appropriate registers.
for UART module registers.
16-2
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Each clocked by either URT_CLK or CLKIN, eliminating a need for an external crystal
Full-duplex asynchronous/synchronous receiver/transmitter channel
24-byte FIFO receiver
— CTS receiver FIFO control
— Receiver FIFO timeout
24-byte FIFO transmitter
Independently programmable receiver and transmitter clock sources
Programmable data format:
— 5–8 data bits plus parity
— Odd, even, no parity, or force parity
— One, one-and-a-half, or two stop bits
Each channel programmable to normal (full-duplex), automatic echo, local loop-back, or remote
loop-back mode
Automatic wake-up mode for multidrop applications
Eight maskable interrupt conditions
Parity, framing, and overrun error detection
False-start bit detection
Line-break detection and generation
Detection of breaks originating in the middle of a character
Start/end break interrupt/status
Autobaud capability
The MCF5272 receiver and transmitter FIFOs have been expanded to 24 bytes.
Interrupts can be programmed to occur at various levels of FIFO fullness on both the receiver and
transmitter.
Autobaud capability has been added to automatically calculate the character transmission rate from
the first received character.
Registers have been added to increase accuracy in clock generation.
Serial Module Overview
Register Descriptions
“Programming,” describe basic UART module programming. The operation of the UART
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
Table 16-1
Freescale Semiconductor
is a memory map
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