MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 203
MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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As
be refined by setting SDCR[INV], which inverts the SDRAM clock. SDCR[REG] must always be cleared
when SDCR[INV] is set.
The incoming data setup time should be inspected during reads. The active clock edge event of SDCLK
now precedes the MCF5272 internal active clock edge event when (REG = 0). This behavior is frequency
dependent. The two following scenarios are possible:
If the delay between shifted SDCLK and following internal system clock edge is shorter than the read
access time of the SDRAM, data is sampled with the true CAS latency.
Freescale Semiconductor
.
Figure 9-6
•
•
Internal
High-speed timing refinement with true CAS latency. See
Low-speed timing refinement with reduced effective CAS latency.
Internal CLK
SDCLK
Data bus
SDCLK
Data
CLK
shows timing relationships between SDCLK and the remaining data and control signals can
If the delay difference between the fastest data signal and the slowest control
signal exceeds half of the clock cycle time, the clock shift can cause
hold-time violations on control signals.
Figure 9-7. Timing Refinement with True CAS Latency and Inverted SDCLK
MCF5272 ColdFire
Figure 9-6. Timing Refinement with Inverted SDCLK
®
Integrated Microprocessor User’s Manual, Rev. 3
Data setup delay
NOTE
Shifted delay of SDCLK
CASL = 2
T
SDCLK_to_CLK
Shifted delay of SDCLK
- T
Figure
acc
< 0 => true CAS latency
Delay SDCLK to CLK
9-7.
SDRAM read access time
SDRAM Controller
9-13
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