MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 507
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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23.9
Table 23-17
1
2
3
4
Figure 23-17
Freescale Semiconductor
P1
P4
P5
P6
Name
P10
P11
For most telecommunications applications the period should be set to 125 µS. Refer to clock generator planning in PLIC
chapter.
Same as DCL0 and FSC0 if internal clock generator configured for pass-through mode.
GDCL1_OUT must be less than 1/20th of the CPU operating frequency. This is to ensure minimum jitter to CODECs that may
be connected to Ports 1,2,3.
Based on generated GDCL1_OUT less than 1/20 of CPU clock frequency.
P2
P3
P7
P8
P9
1, 2
3, 2
4, 2
4, 2
DOUT1, DOUT3
DIN1, DIN3
DFSC[3:1]
DFSC[1:3] period
Delay from rising edge of GDCL1_OUT to rising edge of DFSC[3:1]
Delay from rising edge of GDCL1_OUT to DFSC[3:1] Invalid (output Hold
GDCL1_OUT clock period
GDCL1_OUT pulse-width high
GDCL1_OUT pulse-width low
Delay from rising edge of GDCL1_OUT to Low-Z and valid data on DOUT[1,3]
Delay from rising edge of GDCL1_OUT to DOUT[3:1] Invalid (Output Hold)
Delay from rising edge of GDCL1_OUT to High-Z on DOUT[1,3]
Data valid on DIN[1:3] before falling edge of GDCL1_OUT (setup time)
Data valid on DIN[1:3] after falling edge of GDCL1_OUT (hold time)
GDCL1_OUT
PLIC Module: IDL and GCI Interface Timing Specifications
P2
shows timing for IDL master mode, PLIC ports 1, 2, and 3.
shows IDL master timings listed in
P7
MCF5272 ColdFire
Table 23-17. IDL Master Mode Timing, PLIC Ports 1, 2, and 3
P10
P3
Characteristic
Figure 23-17. IDL Master Timing
P5
®
Integrated Microprocessor User’s Manual, Rev. 3
P11
Table
P1
P6
P4
23-17.
P8
Min
20T
45
45
25
25
—
—
—
2
2
P9
Typ
125
—
—
—
50
50
—
—
—
—
—
Electrical Characteristics
Max
20
55
55
30
30
—
—
—
—
—
% of period
% of period
Unit
nS
nS
nS
nS
nS
µS
nS
nS
23-23
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