MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 361
MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 16
UART Modules
This chapter describes the use of the universal asynchronous/synchronous receiver/transmitters (UARTs)
implemented on the MCF5272 and includes programming examples. All references to UART refer to one
of these modules.
16.1
The MCF5272 contains two independent UARTs. Each UART can be clocked by either URT_CLK or
CLKIN, eliminating the need for an external crystal. As
directly to the CPU and consists of the following:
The serial communication channel provides a full-duplex asynchronous/synchronous receiver and
transmitter deriving an operating frequency from CLKIN or an external clock of the correct frequency
(URT_CLK). The transmitter converts parallel data from the CPU to a serial bit stream, inserting
appropriate start, stop, and parity bits. It outputs the resulting stream on the channel transmitter serial data
output (TxD). See
The receiver converts serial data from the channel receiver serial data input (RxD) to parallel format,
checks for a start, stop, and parity bits, or break conditions, and transfers the assembled character onto the
bus during read operations. The receiver may be polled- or interrupt-driven. See
“Receiver.”
Freescale Semiconductor
•
•
•
•
Serial communication channel
Programmable transmitter and receiver clock generation
Internal channel control logic
Interrupt control logic
Overview
System Integration
Module (SIM)
Controller
Interrupt
Section 16.5.2.1,
MCF5272 ColdFire
Figure 16-1. Simplified Block Diagram
Internal Channel
“Transmitting.”
Interrupt Control
Control Logic
®
Integrated Microprocessor User’s Manual, Rev. 3
Logic
UART
Figure 16-1
Communications
Programmable
Generation
Channel
Clock
Serial
shows, each UART module interfaces
URT_CTS
URT_RTS
URT_RxD
URT_TxD
CLKIN
or
External clock (URT_CLK)
Section 16.5.2.2,
16-1
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